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Memory & Processor Architecture Worksheet

6 min read

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Part 1

Largest Memory

  • What is the largest memory that can have a starting or lowest address of 16000016
    • 16000016→1,441,99210
    • 16000016→0001 0110 0000 0000 0000 00002 → 24 bit number (21 without leading zeroes)
    • Max address space → 224=16,777,216=16MB
    • Remaining space → 16,777,216−1,441,992≈14.63MB

High and Low Addresses

  • What are the high and low addresses of the memory ranges defined by the chip select shown?
    • 5-input active low NAND, where 𝑎26, 𝑎25, and 𝑎23 are inverted
      • 𝑎27→1 (direct input)
      • 𝑎26→0 (inverted)
      • 𝑎25→0 (inverted)
      • 𝑎24→1 (direct input)
      • 𝑎23→0 (inverted)
    • 𝑎27 to 𝑎23 (5 bits) are chip select, 𝑎22 to 𝑎0 (23 bits) are unimportant
    • Low address → 1001 0000 0000 0000 0000 0000 0000→900000016
    • High address → 1001 0111 1111 1111 1111 1111 11110→97FFFFF16

Processor Memory Space

  • What is the processor memory space for the chip in problem 2?
    • 𝑎27 to 𝑎0 is 28 bits
    • 228→268435456→256MB

Memory Device Size

  • What is the memory device size for each chip select in problem 2?
    • 97FFFFF16−900000016
    • 159383551−150994944+1=8388608=8MB

Devices in Processor

  • How many 16K memories can be placed (without overlapping) in the memory space of a processor that has 24 address lines?
    • Processor memory space → 224→16777216=16MB
    • Each device → 16KB=16384bytes
    • Total devices → 1677721616384=1024devices

Active Low Chip Select

  • Using logic gates, design an active low chip select for each of the following situations
    • A 256K memory device starting at address 28000016 in a 4 meg memory space
      • 256𝑘memory→262,144bytes
      • 28000016→2,621,440
      • 4meg space→1MB×4→4194304bytes
      • Address range
        • Low → 10 1000 0000 0000 0000 0000
        • High → 2,621,440+262,144−1=2,883,583=2BFFFF16
        • Bit pattern → 1010, Variables → 𝑎17→𝑎0
    • A memory device in the range 3000016 to 37FFF16 in a 1 meg memory space
      • 1MB→1,048,576bytes→220→20 address lines
      • Low → 0011 0000 0000 0000 0000
      • High → 0011 0111 1111 1111 1111

SRAM & DRAM

  • How many latches are contained in a SRAM that has 20 address lines and 8 data lines
    • Address lines → 220
    • Data lines → 8
    • Latches → 1,048,576×8→8,388,608latches
  • True or false: DRAM is faster than SRAM. Why?
    • False, DRAM has less components and has changing data
  • True or false: DRAM is cheaper per bit than SRAM. Why?
    • True, DRAM (1 transistor + 1 capacitor per bit), SRAM (6 transistors per bit)
  • True or false: More DRAM can be packed into the same area than SRAM. Why?
    • True, less components take up less space
  • Which is usually used for smaller memories, DRAM or SRAM? Why?
    • SRAM, speed

Data Signals

  • When data is passed from a memory chip to the processor, what values do the bus signals 𝑅 and 𝑊 have?
    • 𝑅=0,𝑅=1
    • 𝑊=1,𝑊=0

Class C IPv4

  • What is the subnet and host id of the Class C IPv4 address 194.164.39.2?
    • Class C → 24bits→3bytes
    • Subnet → 194.164.39.0
    • Host ID → 2
  • Taking into account the address for the subnet and broadcast, how many hosts can be present on a Class C IPv4 subnet? Why?
    • Class C has 8 host bits → 28=256 addresses
    • The network and broadcast addresses can’t be used → only 254 addresses are available.

Control Lines

  • A processor uses separate control lines for memory and I/O operations. For each of the scenarios below, determine the values of 𝑅memory,𝑊memory,𝑅I/O,𝑊I/O
    • The processor needs to read data from RAM at address 400016
      • 𝑅memory=1
    • The processor wants to send a command byte to a printer
      • 𝑊I/O=1
    • The processor is checking the status of a keyboard
      • 𝑅I/O=1
    • The processor is storing a variable to main memory
      • 𝑊memory=1
  • What happens if 𝑅memory = 0 and 𝑅I/O = 0 simultaneously? Why is this a problem?
    • Signal conflict → data damage.

Part 2

Registers

  • List the types of registers utilized by the processor an describe their operation.
    • General purpose (accumulators) → stores data for arithmetic/logic
    • Address (pointer) → address to variable in memory
    • Index → string/array processing
    • Stack pointer → points to the top of the stack in memory
    • Instruction pointer → address of the next instruction to be executed
  • Determine the settings of the zero flag, the carry flag, and the sign flag for each of the following 8-bit operations
    • 101101102+010010102→1000000002→Zero=1,Carry=1,Sign=0
    • 010110112+011100102→010011012→Zero=0,Carry=0,Sign=1
    • 100110012+000010002→100100012→Zero=0,Carry=0,Sign=1
  • If registers A, B, and C contain the values 12, 65, and 87 respectively, and they are pushed into the stack in the order A, then B, then C, what values do A, B, and C have if they are pulled from the stack in the order C, then A, then B?
    • Pushed → [12,65,87]
    • Pull → 𝐶=87,𝐴=65,𝐵=12

Processor Architecture

  • List and describe the purpose of each of the components of the processor
    • Bus → provides communication pathways for devices
    • Register → high-speed storage within processor
    • Flag → indicates the result of a processor operation
    • Buffer → temporary storage that handles speed difference between components
    • Stack → stores data during subroutine calls and interrupts
    • I/O Port → interface between processor and I/O devices
  • List and describe the purpose of each of the components of the CPU
    • ALU (arithmetic logic unit) → does math & logic operations
    • CPU Registers → high speed storage accessible by the ALU
    • Instruction Decoder → interprets machine code instructions
    • Internal Data Bus → provides pathways for data within the CPU
    • Control Unit → coordinates and controls CPU operations & send signals
  • What type of instruction might force the processor to flush the pipeline? Why?
    • Branch/conditional jump → branching changes the instruction flow
    • Exceptions → when an exception occurs, the current execution context might need to be saved (and the pipeline flushed)

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